The present disclosure is related to a bipolar junction transistor and more specifically to radiation hard bipolar junction transistors in integrated circuits and their method of manufacture.
Bipolar junction transistors (BJTs) are sensitive to ionizing radiation; such radiation causes junction leakage and gain degradation. Ionizing radiation causes hole-electron pair generation in the oxide layers over the device junctions. Electrons thus generated have very high mobility in oxide and drift toward the device's terminals in picoseconds. Holes, on the other hand, have low mobility and tend to be trapped in the oxide. This causes a trapped positive charge in the oxide, which in turn leads to changes in the depletion layers and surface concentrations in the underlying device structure.
The rates of hole trapping in the oxide vary. The trapping rate determines the device's response to radiation. The trapping rate is influenced by factors such as dose rate, dielectric film stress, oxide defects, applied electric field and passivation layer characteristics. In particular, low dose rate irradiation has been found to degrade BJTs much more rapidly than the moderate dose rates used in qualification testing. See, for example:    (a) E. W. Enlow, R. L. Pease, W. E. Combs, R. D. Schrimpf and R. N. Nowlin, “Response of advanced bipolar processes to ionizing radiation,” IEEE Trans. Nuc. Sci., vol. 38, p. 3049, December 1991;    (b) A. H. Johnston, C. I. Lee and B. G. Rax, “Enhanced damage in bipolar devices at low dose rates: Effects at very low dose rates,” IEEE Trans. Nuc. Sci., vol. 43, p. 1342, December 1996; and    (c) J. L. Titus et al., “Enhanced Low Dose Rate Sensitivity (ELDRS) of Linear Circuits in a Space Environment,” IEEE Trans. Nuc. Sci., vol. 46, p. 1608, December 1999.
This is a somewhat counterintuitive result but has turned into a major issue, as these low dose rates are exactly what is actually encountered in space. In the context of this disclosure, a moderate “qualification” dose rate is in the range of 50–300 rad(Si)/s, while a low dose rate is to the order of 0.01 rad(Si)/s. The reason for using the “qualification” dose rate is a logistical one—a lot qualification to a 300 rad(Si) specification takes an afternoon at 300 rad(Si)/s, and three months at 0.01 rad(Si)/s.
The present disclosure addresses the enhanced sensitivity of BJTs to the low dose rate environment. Radiation sensitivity of the BJT involves inversion of the base surface near the emitter leading to emitter-base junction spreading at the Si/SiO2 interface and higher base current due to increased surface recombination. The hardness of the BJT depends on the hardness of this parasitic MOSFET-like region to inversion to avoid emitter depletion spreading.
The enhanced low dose rate sensitivity (ELDRS) phenomenon is believed to revolve around higher charge trapping rates at the lower dose rates. The phenomenon is not very repeatable, with substantially different results depending on such factors as processing, fabrication facility and bias during irradiation. Transistor-level radiation testing at Intersil Corporation has shown very severe degradation of the low-current gain of the transistor after low dose rate irradiation. FIG. 1 shows a representative figure, taken from unpublished Intersil Corporation data. The figure shows forward beta versus collector current for an NPN device irradiated at 10 mrad(Si)/s at room temperature. The upper curve represents the pre-irradiation data, while the three lower curves represent the 25 krad(Si), 50 krad(Si) and 100 krad(Si) data, respectively. This data indicates that designing parts to be hard in this environment would involve some difficult tradeoffs with power dissipation, as the transistors in a hardened design would need to be operated at collector current levels of one or two orders of magnitude higher than those found in the current designs.
Attempts at hardening commercial processes have included changes to or outright elimination of the passivation layer. See, for example, R. L. Pease et al., “Total-Dose Hardening of a Bipolar-Voltage Comparator,” IEEE Trans. Nuc. Sci., vol. 49, p. 3180, December 2002. Investigation of the effects of dielectric film stress is described in a paper by M. R. Shaneyfelt et al., ‘Impact of Passivation Layers on Enhanced Low-Dose-Rate Sensitivity and Pre-Irradiation Elevated-Temperature Stress Effects in Bipolar Linear IC's,’ IEEE Trans. Nuc. Sci., vol. 49, p. 3171, December 2002. None of these methods have been entirely successful. One method of forming a field plate layer bridging the emitter-base junction and separated therefrom by a thin oxide layer is shown in U.S. Pat. No. 4,590,664.
Another method for hardening junction bipolar transistors in integrated circuits by changing the basic device structure is proposed in this disclosure. The method includes forming a base region in a surface of a collector region of a substrate and an emitter region in the surface of the base region. A mask is applied exposing the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric layer juxtaposed on at least the total surface of the emitter region and adjoining portions of the surface of the base region. A portion of the field plate layer is removed to expose a first portion of the emitter surface. A second dielectric layer is formed over the field plate layer and the exposed portion of the emitter. A portion of the first and second dielectric layers is removed to expose the first portion of the emitter surface and adjoining portions of the field plate layer. A common contact is made to the exposed first portion of the emitter surface and the adjoining portions of the field plate layer.
The resulting integrated circuit includes at least one bipolar junction transistor having a base region in a surface of a collector region and an emitter region in the surface of the base region. A field plate layer is juxtaposed on and separated by a first dielectric layer from adjoining portions of the surface of the base and emitter regions. A common contact is to a first portion of the emitter surface and the juxtaposed adjoining portions of the field plate layer.
Another method of forming a bipolar junction device in an integrated circuit comprises applying a mask exposing the total surface of the emitter region and adjoining portions of the surface of the base region and forming a first dielectric layer over the exposed surfaces. A portion of the first dielectric layer is removed to expose a first portion of the emitter surface. A common contact and field plate are formed to the exposed first portion of the emitter surface and on the first dielectric layer over the emitter-base junction.
In another embodiment, the bipolar junction transistor includes a common contact and field plate layer having a field plate portion juxtaposed on and separated by a first thin dielectric layer from adjoining portions of the surface of the base and emitter regions; and a contact portion extending through the first dielectric layer to a first portion of the emitter surface.
These and other aspects of the present disclosure will become apparent from the following detailed description of the disclosure, when considered in conjunction with accompanying drawings.